Wafer level packaging (WLP) technology provides for the packaging of semiconductor devices at a wafer level. WLP is employed in a variety of technologies including 3D-integrated circuits (IC), chip scale package (CSP) devices, and micro-electro-mechanical systems (MEMS) for enhancing electrical properties and reducing costs. However, there are several limitations to the current WLP technology and the integration of the wafer fabrication and packaging processes it provides. The methods of packaging (e.g., protecting the device and providing interconnections) may not be compatible with the fabrication processes that are used to form the devices. Furthermore, solutions often require complicated packaging schemes that suffer from area/density penalties, contamination issues, and/or structural weakness. In one example, MEMS devices have suffered from a poor mechanical structure at an anchor area due to the lack of control over etch of the sacrificial layer.